In high performance integrated circuit (IC) clock design, the tradeoff between the performance and the power consumption is well-studied. In application-specific integrated circuit (ASIC) design, clock tree topologies are preferred due to their low power profile with less wire demand and flexibility to be combined with low power techniques such as multi-voltage domain design. On the other hand, in high-end microprocessor design, clock topologies with redundancies are preferred due to their tolerances against process variations with the cost of extra wire capacitance. In the clock tree topologies with spines and crosslinks, selected branches are shorted to decrease the skew mismatch in the presence of variations, whereas in clock mesh topologies, every branch is shorted in the design to provide a global improvement of the skew.